IAR Information Center for Arm

If the compiler warning is ignored, the linker will issue an error:

Error[Li005]: no definition for "__get_SB"

• with the option --no_unaligned_access (which limits the available immediate offsets)
• without the option --no_clustering (static clustering leads to larger offsets).

void f(int x) < if (7 - x != 4) < printf("exit 1\n"); return; >if (7 - x != 4) < printf("exit 2\n"); return; >printf("exit 3\n"); return; >

int ff(int *); int f(int i) < switch (i) < case 1: < int j1; i = ff(&j1); i += j1; break; >case 2: < int j2; i = ff(&j2); i += j2; break; >> return i; >

class Other final < public: ~Other() <> >; class Base < public: virtual ~Base() = default; >; template class Derived : public Base < public: // ***** Spurious error Pe766 here ~Derived() override = default; private: Other other; >; // ***** Spurious warning Pe768 here class Derived2 : public Derivedint> <>;

void f(char *p, signed long v, char m) < char tmp[2] = < 4, 2 >; char r; switch (m) < case 1: < *p = ((char)(v)); >break; case 2: < *p = ((char)((v * 255) / 100)); r = ((char)((v * 255) % 100)); if ((r >= 50) && ((*p) < 255)) < (*p)++; >> break; case 3: < *p = ((char)(v)); >break; case 4: < memcpy(p, &tmp[0], 2); >break; case 5: < memcpy(p, &tmp[0], 2); >break; > >

typedef struct refPic < struct refPic *refPic; >refPic; typedef struct < refPic refPic[20]; refPic refPicList[20]; >picBuffer;

struct X < alignas(8) static constexpr short sh[2]; >;

if (((64 - 1u) < (levelState - 1u))) < __set_BASEPRI(64); >State->Level = levelState;

struct S < int i; constexpr S(): i<> <> >; struct X < constexpr X(): p(&u.i) <>// Note: p references inside u S u; int *p; >; struct Y: X < constexpr Y() <>>; constexpr Y y; // Error[Pe2807]: initialization is not constant 

struct A < int x : 8; int y : 8; >; struct A f(int x, int y) < struct A id; id.x = x; // Triggers Go029 erroneously id.y = y; return id; >

templateint n> class Class < public: static long test(long x) < if constexpr(n < 0) < return 0; > else < return 1; > > // Warning[Pe940]: missing return statement at end of non-void function >;

User guide corrections

Miscellaneous

• Available workarounds for device erratas:
  • ARM Cortex-M3 errata 463764
    Core might freeze for SLEEPONEXIT single instruction ISR . More information is available on infocenter.arm.com.
    Workaround generated for functions with attribute __irq with iccarm --enable_hardware_workaround=arm463764 . Supported from EWARM 5.41.
  • ARM Cortex-M3 errata 602117
    LDRD with base in list might result in incorrect base register when interrupted or faulted. From EWARM 5.20.3 the compiler/library avoids the LDRD instruction with the base register in list.
  • ARM Cortex-M3 errata 752419
    ARM Cortex-M4 errata 752770
    Interrupted loads to SP can cause erroneous behaviour. From EWARM 6.21 the compiler/library does not generate LDR SP instructions with writeback to Rn . Otherwise we allow the extra reads because the stack resides in RAM where multiple reads are acceptable.
  • ARM Cortex-M4 errata 776924
    VDIV or VSQRT instructions might not complete correctly when very short ISRs are used. IAR recommends the second workaround proposed by Arm: "Ensure that every interrupt service routine contains more than 2 instructions in addition to the exception return instruction." The background is that the compiler is unaware of interrupts since the Cortex-M architecture does not distinguish between ordinary functions and interrupt functions.
  • ARM Cortex-M7 errata 833872
    Flag setting instructions inside an IT block might cause incorrect execution of subsequent instructions. From EWARM 7.40, the compiler will the skip the IT transformation on this particular code pattern.
  • ARM Cortex-M3 errata 838469
    ARM Cortex-M4 errata 838869
    Store immediate overlapping exception return operation might vector to incorrect interrupt. Follow the guidelines in the errata and implement the workaround proposed by ARM by using __DSB(void) in applicable cases.
  • Functional problem Core.1 in NXP device LPC2478: Incorrect update of the Abort Link register in Thumb state.
    Workaround generated with iccarm --enable_hardware_workaround=NXP_Core.1
  • Functional problem in Stellaris devices: Non-word-aligned write to SRAM can cause an incorrect value to be loaded. More information is available on the Stellaris web site at www.ti.com/stellaris.
    Workaround generated with iccarm --enable_hardware_workaround=LM3S_NWA_SRAM_Write
  • Functional problem in Freescale Semiconductors MC9328MX1 (i.MX1), masks 0L44N, 1L44N, and 2L44N:
    The LDM instruction will in some cases not load the second register correctly. Workaround generated with iccarm --enable_hardware_workaround=920t-ldm2
    NOTE: The libraries in the current EWARM version are not built with this workaround. Use EWARM 6.50.6 and linker option --enable_hardware_workaround=920t-ldm2 to use libraries built with this hardware workaround.